1. Field of the Invention
The present invention relates to a method of forming a fuse, and more particularly, to a method of forming fuse and bonding pad with a single-layered aluminum metal and two photo-etching-processes (PEP).
2. Description of the Prior Art
Aluminum alloys with silicon dioxide (SiO2) dielectrics have been the materials of choice for interconnect systems since the dawn of the integrated circuit (IC) era. These materials were convenient to process using mature subtractive etch processes for metal line patterning. However, as ICs have relentlessly marched down the path towards smaller geometry and to a deep sub-micron generation in the pursuit of increased speed, the traditional Al/SiO2 interconnect system has shown itself to be a limiting factor. Cu-dual damascene architectures with low-k dielectrics are thus developing and becoming the norm now in forming interconnects. Overall, RC delays occurring during signal transmission are reduced and operating performance is improved because Cu has a 40% less resistivity compared with aluminum, and low-k materials reduce the capacitance between interconnections.
In an integrated circuit, each transistor or cell needs to be electrically connected to corresponding metal lines within different metal layers after being formed. Then the transistors are electrically connected to bonding pads through each metal line. After being packaged, the integrated circuit is electrically connected to an external circuit through terminals, which are electrically connected to bonding pads. In a memory device, structures known as fuses are usually formed within the top metal layer. If there are portions of malfunctioning memory cells, word lines, or metal lines in a completed memory device, some redundant cells, redundant word lines, or redundant metal lines are utilized to replace them. The method is to use a laser zip step to sever fuses. Then a laser repair step including laser cutting, laser linking, etc., is used to sever the original electrical connection to the malfunctioning memory cells, word lines, or metal lines, or to form some new electrical connection to compensate the useless memory cells, word lines, or metal lines.
Please refer to FIG. 1 through FIG. 4. FIG. 1 through FIG. 4 are schematic diagrams showing the formation of a fuse 26 on a semiconductor wafer according to the prior art method. As shown in FIG. 1, at least one memory cell (not shown) or at least one transistor (not shown) is formed on a silicon substrate 11 on a semiconductor wafer 10 followed by the formation of individual metal lines 12. Different metal lines 12 are isolated by a first dielectric layer 14.
The metal lines 12 are composed of aluminum or copper. In the case where aluminum is used, a continuous process including deposition, photolithography, and etching is utilized. In the case where copper is used, a dual damascence process is usually utilized. The reason is that aluminum is usually formed by a DC magnetron sputtering process, which is characterized by its poor step coverage ability. In the process generation beyond 0.13 μm, line width is smaller, aspect ratio is relatively increased, and the poor step coverage ability causes a severe problem. Although a high temperature (>400° C.) aluminum process with an improved step coverage ability due to a high surface migration rate at high temperature has been developed, it is not satisfactory. However, aluminum is easily deposited and etched, and is very cheap as well. Thus, aluminum is widely utilized in semiconductor factories. Although the metal lines composed of copper are superior to the metals composed of aluminum in terms of electrical performance, the etching process for copper cannot be done in a chemical way because of the poor volatile ability of copper-chloride-alloy, which is a drawback of copper metal lines. The copper is etched by physical momentum produced by the bombardment of ions in plasma on the copper, hence the copper metal line is formed by the dual damascence process to skip the etching process for copper.
As shown in FIG. 2, a second dielectric layer 16 is formed on the first dielectric layer 14 and the metal lines 12. Then at least one via hole 18 is formed in the second dielectric layer 16. The via hole 18 extends from the top surface of the metal lines 12 up to the top surface of the second dielectric layer 16. After that, a metal layer 22 is formed on the entire surface of the semiconductor wafer 10, and the metal layer 22 fills the via hole 18. It is worth noting that a conductive plug may be formed by a deposition and an etching process followed by the formation of a metal layer. Thereafter a photolithography process is performed by utilizing a photoresist layer (not shown) to define the sites of pads 24 and fuses 26 in the metal layer 22. Finally an anisotropic dry etching process is performed to form a pad 24 and fuse 26 in the metal layer 22.
As shown in FIG. 3, a third dielectric layer 28 is formed on the second dielectric layer 16, the pad 24 and the fuse 26. The third dielectric layer 28, also called as a passivation layer, covers the second dielectric layer 16, the pad 24 and the fuse 26 completely. Then an etching back process is performed from the top surface of the third dielectric layer 28 downwards. It is worth noting that the third dielectric layer 28 is composed of transparent material so the laser beam is able to transmit and sever the fuse 26 in the subsequent laser zip process.
As shown in FIG. 4, a photo-etching-process (PEP) is performed to remove the third dielectric layer 28 on top of the bonding pads 24. The metal material is therefore exposed so the testing and packaging processes can be performed.
Similar to metal lines, the composition material for metal layers is aluminum or copper. That means the fuse 26 is composed of aluminum or copper. If the fuse is composed of copper, an electroplating process is usually used. However, copper is difficult to evaporate during the laser zip process because of its high melting point. A splash phenomenon results and causes difficulty in assuring high reliability. If the fuse is composed of aluminum, its thickness is increased in the process generation beyond 0.13 μm to prevent the occurrence of an open circuit due to the electromigration tendency of aluminum. To increase the thickness of aluminum brings difficulty to the process, and it is difficult to sever the fuse. In the prior art, the energy of laser beam can be adjusted by adjusting the laser spot size. However, the higher the energy of laser beam, the higher probability of damaging the structure underneath. If the composition material in the via hole is aluminum, its poor step coverage ability easily induces problems. It is therefore very important to develop a method of forming a fuse composed of aluminum and to not bring difficulty to the subsequent laser zip process.